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ics for communications quadruple transceiver for s/t interface quat-s peb 2084 version 1.2 data sheet 07.95 t2084-v12-d1-7600
ausgabe 07.95 herausgegeben von siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1995. alle rechte vorbehalten. wichtige hinweise! gew?hr fr die freiheit von rechten dritter leisten wir nur fr bauelemente selbst, nicht fr anwendungen, verfahren und fr die in bauelementen oder baugruppen realisierten schaltungen. mit den angaben werden die bauelemente spezifiziert, nicht eigenschaften zugesichert. lieferm?glichkeiten und technische ?nderun- gen vorbehalten. fragen ber technik, preise und lieferm?g- lichkeiten richten sie bitte an den ihnen n?chstgelegenen vertrieb halbleiter in deutschland oder an unsere landesgesell- schaften im ausland. bauelemente k?nnen aufgrund technischer erfordernisse gefahrstoffe enthalten. aus- knfte darber bitten wir unter angabe des betreffenden typs ebenfalls ber den vertrieb halbleiter einzuholen. die siemens ag ist ein hersteller von cecc- qualifizierten produkten. verpackung bitte benutzen sie die ihnen bekannten ver- werter. wir helfen ihnen auch weiter C wen- den sie sich an ihren fr sie zust?ndigen ver- trieb halbleiter. nach rcksprache nehmen wir verpackungsmaterial sortiert zurck. die transportkosten mssen sie tragen. fr verpackungsmaterial, das unsortiert an uns zurckgeliefert wird oder fr das wir keine rcknahmepflicht haben, mssen wir ihnen die anfallenden kosten in rechnung stellen. bausteine in lebenserhaltenden ger?ten oder systemen mssen ausdrcklich da- fr zugelassen sein! kritische bauelemente 1 des bereichs halblei- ter der siemens ag drfen nur mit ausdrckli- cher schriftlicher genehmigung des bereichs halbleiter der siemens ag in lebenserhalten- den ger?ten oder systemen 2 eingesetzt wer- den. 1 ein kritisches bauelement ist ein in einem lebenserhaltenden ger?t oder system ein- gesetztes bauelement, bei dessen ausfall berechtigter grund zur annahme besteht, da? das lebenserhaltende ger?t oder sy- stem ausf?llt bzw. dessen sicherheit oder wirksamkeit beeintr?chtigt wird. 2 lebenserhaltende ger?te und systeme sind (a) zur chirurgischen einpflanzung in den menschlichen k?rper gedacht, oder (b) untersttzen bzw. erhalten das menschliche leben. sollten sie ausfallen, besteht berechtigter grund zur annahme, da? die gesundheit des anwenders ge- f?hrdet werden kann.
peb 2084 revision history: current version: data sheet 07.95 previous releases: preliminary technical manual 2.94 page (in previous version) page (in current version) subjects (major changes since last revision) 11 10 figure 1, ido = output and input 9 12 pin 40, ido, resistor definition 20 22 boundary scan, sequence of test pins (new) 29 33 push-pull sensing 43 44 state diagram (di ? f3) 55 60 maximum voltage on any pin 56 63 power supply current
peb 2084 table of contents page semiconductor group 4 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.2.1 s/t interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.2.2 iom ? -2 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.2.3 jtag boundary scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.3 individual functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.3.1 transceiver, analog connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.3.2 timing recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.3.3 receive signal oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3.4 activation / deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.3.5 s/t interface frame structures synchronization . . . . . . . . . . . . . . . . . . . . . .29 2.3.5.1 multi-frame generation with a short fsc . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.3.5.2 super-frame (m-bit) generation using ssync (for dect) . . . . . . . . . . . . .31 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.2 push C pull sensing on pin ido . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.3 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.3.1 isdn channels allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.3.2 monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3.3 d-channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.3.4 command/indicate channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.4 activation and deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.4.1 lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.4.2 lt-t mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.4.3 example of activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.5 diagnostic functions, test loop-backs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.6 s and q channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.7 default-use of pin ceb/ssync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 4.1 identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 4.2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.3 loopback register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.4 auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.5 other registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
peb 2084 table of contents page semiconductor group 5 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 5.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.4 recommended oscillator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.6 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.7 iom ? -2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.8 timing of boundary scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 5.9 transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 7 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 iom ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of siemens ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , asm ? , asp ? are trademarks of siemens ag. purchase of siemens i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c-system provided the system conforms to the i 2 c specifications defined by philips. copyright philips 1983.
semiconductor group 6 general information 1overview the peb 2084, quadruple transceiver for s/t interfaces (quat-s), implements four- wire s/t interfaces used to link voice/data digital terminals to pbx subscriber lines and pbx trunk lines to the public isdn. the quat-s is an optimized device for pbx applications but can also be used in hubs and multiplexers. it can handle up to four s/t interfaces simultaneously. while each channel is independently useable as s or t interface. the peb 2084, quat-s, provides electrical and functional link between the analog s/t interface and the isdn-oriented modular (iom-2) interface. it handles the s/t interfaces fully according to ccitt i.430, etsi 300.012, and ansi t1.605 standards. the peb 2084, quat-s, is a cmos device offered in a p-mqfp-44 package. it operates from a single 5 v power supply. other siemens integrated circuits for pbx applications are: peb 20550 extended line card interface controller (elic) peb 2465 signal-processing codec filter with 4 channels (sicofi-4) peb 2096 octal transceiver for u pn interfaces (octat-p) peb 2075 isdn d-channel controller (idec)
semiconductor group 7 general information example for an integrated analog / digital pbx application itb05392 quat-s peb 2084 peb 2096 octat -p sicofi -4 peb 2465 slic slic r/t 2048 kbit/s elic d arbiter sacco-a cfi 00 pcm 1 2 3 peb 20550 t ss peb 2075 idec memory p 4 x d cannel p interface pn u te 7 te 0 te 1 te 16 8 x s 8 x u pn 16 x t/r 0 7 8 x t co sacco-b r s 0 r te 0 te 7 pcm 2084 peb quat-s signaling iom -2 r r r iom -2 r iom -2 r
p-mqfp-44-2 semiconductor group 8 07.95 quadruple transceiver for s/t interface (quat-s) peb 2084 cmos 1.1 features ? four full duplex (b1 + b2 + d) s/t interface transceivers, each equipped with the following functions: C analog s/t interfaces fully according to the ccitt i.430, etsi 300.012 and ansi t1.605 standards. C 192 kbit/s transmission rate C receive timing recovery C conversion between pseudo-ternary and binary codes C conversion between s/t and iom-2 frame structures C activation / deactivation procedures, triggered by primitives received over the iom - 2 interface or by info received from the line (e.g. detection of info1) C access to s and q bits of s/t interface C execution of test loops C loop length up to 1.5 km (point-to-point) C frame alignment in trunk applications with maximum wander of 50 m s C logical s/t interface functions identical to peb 2081, sbcx, for line card applications. C analog s/t line transceivers identical to peb 2081, sbcx. ? iom-2 interface ? d-channel access control ? support for jtag boundary scan test ?1 m cmos technology with low power consumption ? + 5 v power supply ? p-mqfp-44 package type ordering code package peb 2084 h Q6701-H6481 p-mqfp-44-2 (smd)
peb 2084 semiconductor group 9 1.2 logic symbol figure 1 quat-s logic symbol
peb 2084 semiconductor group 10 1.3 pin configuration (top view) p-mqfp-44-2
peb 2084 semiconductor group 11 1.4 pin description pin no. symbol input (i) output (o) function 29, 30 32, 33 27, 26 24, 23 5, 4 2, 1 7, 8 10, 11 sr0a,b sx0a,b sr1a,b sx1a,b sr2a,b sx2a,b sr3a,b sx3a,b i o i o i o i o s/t interface a: positive, b: negative no. 0: differential input no. 0: differential output no. 1: differential input no. 1: differential output no. 2: differential input no. 2: differential output no. 3: differential input no. 3: differential output 43 42 41 40 39 fsc dcl idi ido ics i i i o/i i iom ? - 2 interface frame synchronization clock (8 khz) data clock iom interface data input: data downstream in lt-s data upstream in lt-t iom interface data output: data upstream in lt-s data downstream in lt-t output open-drain: resistor to v dd push-pull: resistor to v ss resistor = 100 k w to 1 m w refer to push-pull sensing, chapter 3.2 iom interface channel select (pin-strapping) 0: channels 0 though 3 selected 1: channels 4 through 7 selected 16 15 14 13 tms tck tdi tdo i i i o jtag boundary scan test interface test mode select test clock 6.25 mhz test data input test data output 20 21 xtal1 xtal2 i o oscillator or 7.68 mhz clock input oscillator output
peb 2084 semiconductor group 12 36 clk1/ ids o/i clk1: clock output 1.536 mhz synchronized to the trunk line (after reset in high impedance state, only activated by programming configuration register) ids: iom-interface data rate select during hw reset (pin-strapping) 0: double dcl (normal iom-2 interface) 1: single dcl the value of the input is sampled by the falling edge of rst. afterwards the pin may be used for clk1 functions. 35 clk2 o 7.68 mhz clock output 38 rst i reset, active high 17 ceb / ssync i/o / i ceb: common echo bit for collision resolution in logical subscriber lt-s bus configurations (open drain output, external pull-up resistor required.) ssync : superframe synchronization input 18 drdy o d-channel ready signal to control hdlc hardware in lt-t mode (open-drain or push-pull operation identical to pin ido) 6, 12, 22, 28, 34, 44 3, 9, 19, 25, 31, 37 v dd v ss i i + 5 v power supply reference ground 1.4 pin description (contd) pin no. symbol input (i) output (o) function
peb 2084 semiconductor group 13 2 functional description the peb 2084, quat-s, performs the layer-1 functions of the isdn basic access for four s/t interfaces. 2.1 device architecture the quat-s contains the following functional blocks: refer to figure 2 ? four line transceivers with analog s/t interfaces ? one digital iom-2 interface ? frame structure converter between the iom-2 interface and the s/t interfaces ? jtag boundary scan test interface ? clocking, reset and initialization block figure 2 quat-s device architecture
peb 2084 semiconductor group 14 2.2 interfaces peb 2084, quat-s, provides four independent s/t interfaces, one iom-2 interface and one jtag boundary scan test interface. 2.2.1 s/t interface frame structure one frame consists of 48 bits, at a nominal bit rate of 192 kbit/s. thus each frame carries two octets of b1, two octets of b2 and 4 bits of d-channel, according to the b1+b2+d structure defined for the isdn basic access (the total user data rate is 144 kbit/s). the beginning of the frame is marked with a f-bit using a code violation (no mark inversion). the frame structures for data downstream (from network to subscriber) and for data upstream (from subscriber to network) are shown in figure 3 . figure 3 frame structure at reference points s and t (ccitt i.430) the e-bit (= echo bit to the d-channel bit) can be controlled via c/i channel and may be used to carry the available / blocked information sent by elic, peb 20550. refer to chapter 3.3.3 . itd02330 dl. 0 1 0 l. f b1 edaf n a b2 edm b1 s d eb2 e d l. f l. 48 bits in 250 s l. f l. d l. b2 l. d l. b1 l. d l. b2 a l. f l. d l. b1 fl. l. d f = framing bit dc balancing bit = l d-channel bit = d d-echo-channel bit = e auxiliary framing bit or q-bit = f a bit set to a binary value n = n b1 = bit within b channel b2 = a = bit used for activation s = subchannel sc1 through sc5 bit position m = multiframing bit bit within b channel t f a = 1 2 2 bits offset nt te nt te 0 1 0
peb 2084 semiconductor group 15 coding the quat-s uses a pseudo-ternary coding technique on the s/t interface (with a 100% pulse width) according to ccitt i.430 recommendation. a binary 1 corresponds to a neutral level (space = no current) on the s/t line, binary 0s are coded as alternating positive and negative pulses (= marks), figure 4 . code violation (cv) is caused by two successive pulses with the same polarity (= no mark inversion). figure 4 s/t interface line code for details refer to technical manual peb 2081, sbcx.
peb 2084 semiconductor group 16 interface configurations the quat-s provides four s/t interfaces for different applications, see figure 5 : ? subscribers connection to pbx (lt-s mode) for different line configurations: C point-to-point C short passive bus C extended passive bus ? pbx connection to co trunk (lt-t mode) figure 5 s/t interface configurations the t interface is physically identical to the s interface.
peb 2084 semiconductor group 17 2.2.2 iom ? -2 system interface the peb 2084, quat-s, is equipped with a digital isdn oriented modular (iom-2) interface, for interconnection with other telecommunication ics, such as idec (peb 2075), epic (peb 2055) and elic (peb 20550). epic and elic represent the first switching stage towards the exchange system. figure 6 system integration, iom ? -2 interface interface signals the iom-2 interface is a four-wire serial interface which comprises two data lines and two clock lines for synchronization. refer to figure 6 . data is carried over data upstream (du) and data downstream (dd) lines. the downstream and upstream directions are always seen with respect to the exchange. downstream refers to the information flow from the central exchange via pbx to the subscriber and upstream vice versa.
peb 2084 semiconductor group 18 thus, depending on the programmable quat-s mode, the data lines idi and ido get different meanings: idi (iom interface data input) = data downstream in lt-s = data upstream in lt-t ido (iom-2 interface data output) = data upstream in lt-s = data downstream in lt-t the data is clocked by data clock (dcl) that operates at single or double data rate. the selection is done by pinstrapping (clk1/ids). the iom frames are delimited by an 8 khz frame synchronization clock (fsc). the fsc rising edge indicates the start of an iom - 2 frame. the iom-2 interface specification describes open drain data lines with external pull-up resistors. however, if operation is logically point-to-point, tristate operation is possible as well. frame structure one iom-2 frame typically contains 8 iom channels (sub-frames). the isdn user data rate is 144 kbit/s (b1 + b2 + d). the data is transmitted transparently synchronously and in phase in both directions over the iom-2 interface using time division multiplexing within the 125 m s iom-2 interface frame. refer to figure 7 . quat-s requires iom-2 frame consisting of n complete isdn channels (with 32 bits per channel); n = 4, 5, 6, 16. nominal bit rate of data (idi and ido) 1024 kbit/s 4096 kbit/s nominal frequency of dcl 2048 khz 8192 khz selectable frequency of dcl 1024 khz 4096 khz nominal frequency of fsc 8 khz
peb 2084 semiconductor group 19 figure 7 multiplexed frame structure of the iom-2 interface in lt mode with 2048 kbit/s data rate each iom isdn channel consists of a total of 32 bits, or four octets: b1 (8 bits) + b2 (8 bits) + d (2 bits) plus 14 bits for intercommunication. ? two 8-bit b1 and b2 channels for voice and data communication with a data rate of 64 kbit/s each, ? one 8-bit monitor channel for transferring maintenance information, ? one 2-bit d-channel for data transfer (e.g. signalling) with a data rate of 16 kbit/s ? four command/indication (c/i) bits for controlling layer-1 functions. ? two bits for handling the monitor channel: mr an mx (hand shake control). the user data rate is 144 kbit/s (b1 + b2 + d). monitor channels the monitor channel is used to convey message oriented local functions such as software programming or access to internal registers via a layer-2 controller (icc, elic,). there is a defined handshake procedure between the monitor channel transmitter and the receiver in order to ensure a safe data transfer over the iom-2 interface. 8 bits 8 bits 8 bits 2 4 bits 1 1 b1 channel b2 channel monitor channel d ch. command/ indication mr mx itd04319 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 b1 b2 monitor d c/i mm rx fsc dcl du dd ch0 ch0 s 125 r iom r iom
peb 2084 semiconductor group 20 the monitor channel operates on an asynchronous basis. while data transfer on the bus takes place synchronized to the frame, the data flow is controlled by a handshake procedure using the monitor channel receive bit (mr) and the monitor channel transmit bit (mx). for example: data is placed onto the monitor channel and the mx bit is activated (active low). this data will be transmitted repeatedly once per 8 khz frame until the transfer is acknowledged via the mr bit. the monitor channel is in an idle condition when the mx bit is inactive in two or more consecutive frames (indication of end of message eom). the monitor channel is also used to convey s and q maintenance bits information (s/q channel). the peb 2084, quat-s, handles four monitor channels allocated to its four s/t interfaces. the implemented monitor protocol is according to the iom interface specification, rev. 2. for more details and an example refer to chapter 3.3.2. d-channels the d-channels are switched transparently between the s/t interfaces and the iom-2 interface. depending on the data load on a line card, different pbx architectures can be implemented for d-channel handling in lt-s applications: for decentral signalling, up to 32 subscribers can be served with only one special hdlc controller which is integrated in the peb 20550, elic (sacco-a). for intensive data packet handling in lt-s mode (e.g. in pc networks) or in lt-t applications, additional hdlc controllers such as hscx, idec, escc 2 or 8 or munich 32 may be connected to the iom-2 interface. if a d-channel collision resolution according to ccitt i.430 is required, the quat-s offers a strobe signal to control the connected hdlc (lapd) controller. for operational description refer to chapter 3.3.3. c/i-channels a c/i-channel is used for communication between the peb 2084, quat-s, and a processor via a layer-2 device, to control and monitor layer-1 functions (activation/deactivation and additional control functions). the layer-2 device monitors the layer-1 indication continuously and indicates a change if a new code is found to be valid in two consecutive iom frames (double last look criterion). the codes originated by layer-2 devices are called commands, those originated by the peb 2084, quat-s, are called indications. the peb 2084, quat-s, handles four c/i-channels; one for each s/t transceiver. for a list of the c/i codes and their use refer to chapter 3.6 .
peb 2084 semiconductor group 21 2.2.3 jtag boundary scan test interface the quat-s provides a boundary scan support for a cost effective board testing. it consists of: C complete boundary scan for 11 signals (pins) according to ieee std. 1149.1 specification C test access port controller (tap) C four dedicated pins (tck, tms, tdi, tdo) C one 32-bit idcode register C specific functions for sxna,b boundary scan the following quat-s pins are included in the boundary scan: fsc, dcl, idi, ido, rst, ics, ceb, drdy, clk1, clk2 and xtal1. depending on the pin functionality one or two boundary scan cells are provided. when the tap controller is in the appropriate mode data is shifted into/ out of the boundary scan via the pins tdi/tdo using the 6.25 mhz clock on pin tck. the quat-s pins are included in the boundary scan in the following sequence: pin type number of boundary scan cells usage input 1 input output 2 output, enable boundary scan number tdi CC> pin number pin name type number of scan cells 143fsci1 242dcli1 341idii1 440idoo2+1 539icsi1 638rsti1 7 36 clk1/ids o/i 2 + 1 835clk2o2 920xtal1i1 10 18 drdy o 2 11 17 ceb/ssync i/o 1 + 2
peb 2084 semiconductor group 22 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee std. 1149.1. transitions on the pin tms cause the tap controller to perform a state change. following the standard definition five instructions are executable. tap controller instructions: note: the instructions tm1 and tm2 require 7.68 mhz at xtal1. extest is used to examine the board interconnections. when the tap controller is in the state update dr, all output pins are updated with the falling edge of tck. when it has entered state capture dr the levels of all input pins are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state update dr, all inputs are updated internally with the falling edge of tck. when it has entered state capture dr the levels of all outputs are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. 0001 (intest) is the default value of the instruction register. sample / preload provides a snap-shot of the pin level during normal operation or is used to preload (tdi) / shift out (tdo) the boundary scan with a test vector. both activities are transparent to the system functionality. note: the input pin xtal1 should not be evaluated. the input frequency (7.68 mhz) is not synchronous to tck (6.25 mhz) which may cause not predictable snap-shots on the pin xtal1. code instruction function 0000 extest external testing 0001 intest internal testing 0010 sample/preload snap-shot testing 0011 idcode reading id code 0100 test mode tm1 single pulses (2 khz) on sxna,b 0101 test mode tm2 continuous pulses (96 khz) on sxna,b 11xx bypass bypass operation
peb 2084 semiconductor group 23 idcode register the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacture code (11 bits). the lsb is fixed to 1. note: in the state test logic reset the code 0011 is loaded into the instruction code register. test modes tm1 and tm2 two different pulse types at the line interface sxna,b are selectable: 2 khz single pulses or 96 khz continuous pulses, figure 8. figure 8 test pulse wave forms bypass , a bit entering tdi is shifted to tdo after one tck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. version device code manufacture code output 0001 0000 0000 0010 0000 0000 1000 001 1 ? tdo
peb 2084 semiconductor group 24 2.3 individual functions 2.3.1 transceiver, analog connections the receiver input stages consist of a differential amplifier, followed by a peak detector and a set of comparators. additional noise immunity is achieved by digital oversampling after the comparators, meaning that the sampling of the received bit is controlled digitally and dependent on the mode (configuration register). the peak detector requires at most 2 m s to reach the peak value while storing the peak level for at least 250 m s. the data detection thresholds are chosen to 35 % of the peak voltage to increase the performance in extended passive bus configurations. however they are never lower than 85 mv. the level detector monitors the line input signals to detect whether an information is present. in lt-s analog loop-back mode the level detector monitors its own loop signal and an incoming signal is not recognized. figure 9 receiver functional blocks the transmitter stage consists of two identical current limited voltage sources, one for each polarity of output pulses, in order to achieve a ternary pulse shaping. a voltage of 2.1 v is delivered between sxna and sxnb, which yields a current of 7.5 ma over 280 w .
peb 2084 semiconductor group 25 . figure 10 transmitter functional block external transformers of the ratio 2:1 are needed in receive and transmit directions to provide for isolation and transform voltage levels according to ccitt recommendations i.430. the quat-s also needs external circuitry for impedance matching, overvoltage protection and electromagnetic compatibility (emc) for its connection to the 4-wire s/t interface. figure 11 quat-s external circuitry
peb 2084 semiconductor group 26 note: the actual values of the external resistors depend on the selected transformer. the resistor values are optimal for an ideal transformer ( r cu = 0). line termination ( r t ) is applied to the last te on the s bus only. the transmitter of the quat-s is identical to that of sbcx, hence the line interface circuitry should be the same. the external resistors (20 40 w ) are required in order to adjust the output voltage to the pulse mask (nominal 750 mv according to ccitt i.430) on the one hand and in order to meet the output impedance of a minimum of 20 w (transmission of a binary one according to ccitt i.430) on the other hand. the quat-s has a symmetrical receiver. useful hints on how to design the external interface circuitry are contained in the application note s/t interface circuitry using the peb 2080, sbc, or peb 2085, isac - s from 12.89. 2.3.2 timing recovery lt-s mode (configuration register: mode = 0) in the lt-s mode the quat-s is the clock master to all connected tes. the transmit pll (xpll) synchronizes the 192 khz transmit bit clock to the iom-2 clock fsc (8 khz) derived from the oscillator clock. when the oscillator clock is synchronous to fsc (fixed divider ratio of 960 from 7.68 mhz clock) the xpll will not perform any tracking after having locked the phase, i.e. the input jitter on clocks xtal and fsc will not be increased, see figure 12. figure 12 block diagram of xpll
peb 2084 semiconductor group 27 in the receive direction two cases have to be distinguished depending on the bus configuration: C short passive bus configuration (configuration register: c/w = 1) the 192 khz receive bit clock is identical to the transmit bit clock. the sampling instant for the receive bits is shifted by 4.6 m s with respect to the transmit bit clock. according to ccitt i.430 the receive frame shall be shifted (delayed) by two bits with respect to the transmit frame. C point-to-point or extended passive bus configurations (configuration register: c/w = 0) the 192 khz receive bit clock is recovered (via pll) from the receive data stream on the s interface. according to ccitt i.430 the receive frame can be shifted by 2 to 8 bits with respect to the transmit frame. however other shifts are allowed by the quat-s as well; including 0. lt-t mode (configuration register: mode = 1) in lt-t applications the quat-s is a clock slave to the central office clock, which is always the master. thus a pbx clock system must be locked up with the co clock system. the 192 khz receive bit clock is recovered (via pll) from the receive data stream on the t interface. 2.3.3 receive signal oversampling the receive signal is sampled several times (oversampling) inside the receive clock period, and a majority logic is used to reduce the bit error rate in severe conditions. as illustrated in figure 13 , each received bit is sampled 29 times at 7.68 mhz clock intervals inside the estimated bit window. the samples obtained are compared against a threshold of 50 % with respect to the signal stored by the peak detector. if at least 16 samples have an amplitude exceeding the set threshold, a logical 0 is considered to be detected; otherwise a logical 1 (no signal) is considered to be detected.
peb 2084 semiconductor group 28 figure 13 receive signal oversampling on s and t interfaces the pll also provides a synchronous 1.536 mhz clock (adaptive timing recovery), which can be used to synchronize the pcm clocks of the peb 20550, elic, by means of a xtal controlled pll circuit. refer to figure 14. figure 14 clock system in lt-s and lt-t modes itd02361 27 30 31 24 21 22 26 29 20 23 11 8 17 14 9 7 12 19 18 13 15 16 14 3 5 6 2 33 35 34 32 40 39 38 37 36 28 25 v sr2 sr1 v v tr1 tr2 v derived 192-khz receive bit period 10 - or 0 v
peb 2084 semiconductor group 29 since the elic generates the iom-2 clocks (fsc, dcl) for all connected layer-1 and layer-2 devices, the loop is closed. if several layer-1 devices are operated in lt-t mode, only one device (one channel in a quat-s) may be selected (configuration register, bit rclk) to deliver the reference clock. the receive pll performs tracking every 250 m s after detecting a phase difference between the f/l transition of the receive signal and the recovered clock. a phase adjustment is done by adding or subtracting 65 ns to or from the 1.536 mhz clock cycle. elastic buffer the two interfaces (iom-2 and s/t) of the quat-s require a buffer to compensate for the differences in bit rate between the two interfaces as well as the different round trip delays of various wiring configurations. the quat-s enables intermediate storage of 3 b1, 3 b2 and 6 d-bits for phase difference and wander absorption. moreover, the buffer is designed as a wander-tolerant system, required in lt-t modes where the quat-s is a slave to both interfaces and the data clocks of the two interfaces have a time dependent phase relationship. the elastic buffer of the quat-s compensates for a maximum phase wander of 50 m s peak-to-peak and a slip detector indicates when this limit is exceeded. setting the c/w-bit in the configuration register gives a warning when a slip of 25 m s is exceeded. an indication (slip detected) is released in the c/i channel. however the data may be lost. the phase relationship between the iom-2 interface and the s/t interface is arbitrary in this case. the transmit frame is shifted (delayed) by two bits with respect to the receive frame. 2.3.4 activation / deactivation an incorporated finite state machine controls the activation and deactivation procedures and communicates with the layer-2 unit via the iom-2 c/i channel. each of the four c/i channels is allocated to its corresponding s/t line interface. refer to chapter 3.6. 2.3.5 s/t interface frame structures synchronization the quat-s supports two different kinds of frame structures: a) a multi-frame consisting of 20 consecutive s/t frames. b) a super-frame consisting of 2 n (n = 1, 2, ) consecutive s/t frames. both frames provide an extra layer-1 capacity for information transmission in both application modes: lt-t and lt-s (refer to chapter 3.6 , access to s and q channels).
peb 2084 semiconductor group 30 2.3.5.1 multi-frame generation with a short fsc the quat-s synchronizes to a multi-frame structure according to ccitt recommendation i.430. in lt-s application mode the s interface multi-frame (20 250 m s = 5 ms period) can be generated by a master device (e.g. elic) by inserting a short fsc pulse. an external strobe on the pin ceb/ssync can be used for simple terminal synchronization. a short fsc pulse has a width of one dcl clock whereas a normal fsc pulse has a width of at least two dcl clocks. the quat-s samples the fsc input with the second falling edge of dcl clock in the very first bit positions of the frame. if the sampled bit is zero the s/t interface transmit frame, including multi-frame, is reset. the frame relationship between iom-2 interface (fsc) and s/t interface is shown in the following figures. figure 15 multi-frame generation with a short fsc
peb 2084 semiconductor group 31 2.3.5.2 super-frame (m-bit) generation using ssync (for dect) a zero pulse on the ssync input pin forces the quat-s to send m = 1 synchronously on all four s/t interfaces. (useful with mfd = 1 only.) figure 16 m-bit generation using ssync in lt-t mode the quat-s synchronizes to the received f a -bit inversions and m-bits. when the synchronization is not achieved or lost, it mirrors the received f a -bits. multi-frame synchronization is achieved after two complete multi-frames have been detected with reference to f a /n-bit and m-bit positions. multi-frame synchronization is lost after two or more bit errors in f a /n-bit and m-bit positions have been detected in consequence, i.e. without a complete valid multi-frame in between. the multi-frame synchronization can be disabled by programming the configuration register: mfd = 1.
peb 2084 semiconductor group 32 3 operational description all procedures required for data transmission over the s/t interface are implemented. these comprise the s/t interface frame and multiframe synchronization, activation/deactivation procedure, and timing requirements such as bit rate and jitter. for a correct functionality of the quat-s the following operational precautions must be taken: 3.1 reset at power up, a reset pulse (rst) should be applied to bring the line interfaces of the peb 2084, quat-s, to the state reset. no clocks are required during that procedure. after that the peb 2084, quat-s, may be operated according to the state diagram, each line interface controlled via the corresponding c/i channel. 3.2 push C pull sensing on pin ido the quat-s senses whether an external pull-up resistor (100 k w to 1 m w ) is connected to the pin ido. the sensing is done after reset within the following two iom frames in the monitor channel. the pin is pulled low for one bit and then switched to tristate. if the voltage level at idp0 rises in the next bit to high, quat-s interprets this behaviour as an external pull up being connected to the pin and remains as open collector. if the level stays at low quat-s switches to push-pull. however, actions of other device on this line or crosstalk from other lines during the sensing procedure may falsify the result. (a pull down resistor of 100 k w to 1 m w may improve the correctness of the sensing). this feature is useful if multiple transmitters are connected to the same iom-2 interface, e.g. quat-s with an idec. 3.3 iom ? -2 interface 3.3.1 isdn channels allocation the allocation between s/t line interfaces and the iom-2 isdn channels is according to their numbers with an offset of four or zero. the offset can be selected via pin ics by pin strapping, i.e. for ics = 0 the srx0a,b is allocated to iom channel 0, and so on, for ics = 1 the srx0a,b is allocated to iom channel 4, and so on. for detailed electrical definition refer to the chapter 5 and the iom interface specification, rev. 2. as described in chapter 2.2.2 , each basic isdn channel consists of five different communication channels: two voice channels, one monitor channel (incl. mr and mx bits), one d-channel and one command/indication (c/i) channel.
peb 2084 semiconductor group 33 3.3.2 monitor channel before starting a data transmission to the quat-s, a microprocessor must verify that the transmitter of the quat-s is inactive, i.e. that a previous transmission has been terminated. the quat-s has a monitor transmitter time out function of minimum 4 ms implemented. this prevents the monitor message to be transmitted continuously if the monitor data wont be acknowledged by the receiver. first the identification register of the quat-s may be read. two bytes are transmitted to the quat-s and as a result of the read operation two bytes are returned to the controller. in case of a write operation the data is only acknowledged and no data is returned from the quat-s to the controller. the first byte of the data transmitted to the quat-s always indicates the type of the desired monitor operation (i.e. read or write to the internal registers). the example shows the typical register access of the elic and gives a feeling about the important bits. the elic uses a 16-byte fifo for transmission and reception of the monitor data. therefore the user doesnt need to provide routines for the handshake protocol. an example for a communication between a m p, an elic and the quat-s is shown in figures 17 and 18.
peb 2084 semiconductor group 34 figure 17 monitor channel handling: m p ? elic ? quat-s a detailed description of the hand-shake procedure using mx and mr bits is shown in figure 18.
peb 2084 semiconductor group 35 figure 18 monitor channel handling: hand-shake by the use of mx and mr bits (lt-s mode) quat-s in lt-s mode data downstream: mx-bit at elic ? mr-bit at quat-s data upstream: mx-bit at quat-s ? mr-bit at elic quat-s in lt-t mode data downstream: mx-bit at quat-s ? mr-bit at elic data upstream: mx-bit at elic ? mr-bit at quat-s
peb 2084 semiconductor group 36 3.3.3 d-channel handling decentral d-channel handling in a pbx depends on quat-s application mode: lt-s or lt-t. lt-s mode . configuration register, mode = 0. it is used in pbx applications with only one signalling controller (hdlc) used for up to 32 isdn subscribers in order to minimize system costs. a terminal is allowed to send data only if the signalling controller is ready to receive data. the d-channel access can be controlled via a central d-channel arbiter unit integrated in the peb 20550, elic, or according to ccitt i.430 via an arbitration logic in the quat-s. d-channel arbitration via elic . auxiliary register, dcm(1:0) = 11. elic, peb 20550, informs the quat-s whether the signalling controller (sacco-a) is ready to receive data. it sends commands (c/i) to individual quat-s channels: c/i = 1100 h (e.g. 1000 h ) indicates that the d-channel is available and can be used. c/i = 1100 h indicates that the d-channel currently can not be used (is blocked) as the signalling controller is allocated to an other terminal. the quat-s controls the connected terminal transmitters (e.g. isac-s, sbcx, isac - s te) via its s interfaces accordingly. it translates the information available or blocked by setting the e-bit on the s interface. e = d indicates to the terminal that its hdlc controller can send data. e = d indicates that the hdlc controller may not send data or has to abort sending data. figure 19 quat-s in lt-s mode with a d-channel access via elic d-channel arbiter
peb 2084 semiconductor group 37 the codes (c/i = 1100 h and 1100 h ) can only be used when the quat-s is in the state g3 activated (during info 4 transmission). refer to chapter 3.6. for a detailed description of the d-channel arbiter refer to elic, peb 20550, technical manual 9.93, page 54, chapter 2.2.8. d-channel access according to ccitt i.430 (star configuration) the d-channel access is arbitrated among the terminals themselves, if the quat-s auxiliary register is programmed to dcm(1:0) = 10. figure 20 quat-s in lt-s mode supporting arbitration according to ccitt i.430 the d-channel access control is established as a logical passive bus structure. all received d-channels are anded and the resulting value (internally connected to the pin ceb) is sent back as echo bit on all involved s/t interfaces. if more quat-s work in parallel the ceb pins (open drain output) are wired via an external pull-up resistor to v dd . the short passive bus, a system of multiple tes accessing a single d-channel, is extended to multiple physical s lines still representing a single logical short passive bus. it is a system with multiple b-channels using a single d-channel. only the winning d-channel reaches the elic. the other d-channels remain blocked until a te encounters 8 (10) e-bits equal to the d-bit in a row.
peb 2084 semiconductor group 38 the elic d-channel arbiter doesnt work in this application as an arbiter (all channels are permanently sent the c/i command available = 1000 h ), it only detects the winning d-channel on the iom interface and controls the connected labd controller (sacco - a). lt-t mode configuration register, bit 0: mode = 1 d-channel collision resolution is always controlled according to ccitt i.430. four-channel lt-t applications the pin drdy conveys control information synchronous to the d-channel timeslots to control peb 2075, idec, if the auxiliary register, bits dcm(1:0) = 10. stop when drdy = 0, go when drdy = 1. figure 21 quat-s in lt-t mode with idec for four-channel applications
peb 2084 semiconductor group 39 single-channel lt-t applications quat-s can also be used in a mixed mode, e.g. by programming three channels in lt - s mode and one channel in lt-t mode. the auxiliary register of only one channel can be programmed to dcm(1:0) = 11 and the configuration register pin rclk to 1. whereas the subscriber d-channels are handled by the d-channel arbiter and sacco - a in elic (as described in chapter lt-s mode), the trunk d-channel is handled by the quat-s arbitration logic and sacco-b in elic. if the echo bit differs from the d-bit then quat-s stops sacco-b: drdy = 1, else sacco-b may send data: drdy = 0. pin drdy conveys control information asynchronous to the d-channel timeslot. this mode is applicable to single channel lt-t applications only. figure 22 quat-s with sacco-b for single-channel lt-t applications
peb 2084 semiconductor group 40 clock generation for the above application is shown in figure 14. 3.3.4 command/indicate channel the exchange of control information in the c/i channel is state oriented. this means that a code in the c/i channel is repeated in every iom frame until a next change is necessary. a new code must be found in two consecutive iom frames to be considered as valid (double last look criterion). c/i commands trigger quat-s layer-1 state machine in accordance with ccitt i.430. for a list of the c/i codes and their use refer to chapter 3.6. 3.4 activation and deactivation an internal finite state machine of the peb 2084, quat-s, controls the activation/deactivation procedures, switching of loops and transmission of special pulse patterns. such actions can be initiated by primitives (infos) on the s/t interface or by control codes (c/i) sent over the iom-2 interface. the iom-2 interface should be kept active in both application modes, lt-s and lt-t, for the quat-s is always ready to transmit and receive messages. depending on the application mode and the transfer direction the quat-s state machines support about 20 different codes in conditional and unconditional states: lt-s mode c/i codes data downstream = commands: reset, test mode, activate req.,.. data upstream = indications: not sync., code violation, timer out,.. states: deactivated, activated, pending, lost framing, test mode. the state diagram is shown in figure 23. lt-t mode c/i codes for data upstream = commands: reset, test, activate request,.. data downstream = indications: command x acknowledged,.. conditional states: power up, pending deactivation, synchronized, slip detected,.. the state diagram is shown in figure 24. unconditional states can be entered from any conditional state and should be left with the command tim: loop closed, test mode, reset state,.. the state diagram is shown in figure 25. the activation and deactivation procedures implemented in the peb 2084, quat-s, correspond with those implemented in the peb 2081, sbcx.
peb 2084 semiconductor group 41 3.4.1 lt-s mode (x) unconditional commands command / indication codes commands (downstream) lt-s mode abbreviation code remark deactivate request dr 0000 (x) reset res 0001 (x) test mode 1 tm1 0010 transmission of pseudo-ternary pulses at 2 khz frequency (x) test mode 2 tm2 0011 transmission of pseudo-ternary pulses at 96 khz frequency (x) activate request ar 1000 activate indication ai 1100 transmission of transparent info acc. to state diagram with inverted d-channel mirrored back in e-channel activate request loop arl 1010 activation request for loop 2 deactivate confirmation dc 1111 deactivation acknowledgment, quiescent state indications (upstream) lt-s mode abbreviation code remark timing tim 0000 resynchronizing rsy 0100 receiver is not synchronous activate request ar 1000 info 1 received code violation received cvr 1011 after each multi-frame the receipt of at least one illegal code violation is indicated four times. this function must be enabled by setting the rcve-bit in the configuration register. activate indication ai 1100 synchronous receiver deactivate indication di 1111 timer (32 ms) expired or info 0 received after deactivation request
peb 2084 semiconductor group 42 figure 23 quat-s state diagram of lt-s mode note: 1) ard stands for ar or arl 2) only if dcm (1:0) = 11
peb 2084 semiconductor group 43 figure 24 quat-s state diagram in the lt-t mode, conditional states note: 1) = tm1 and tm2 and res and arl 2) al p stand for ai8 or al10 3) ar p tmi stands for ar8 or ar10 4) tmi stands for tm1 or tm2
peb 2084 semiconductor group 44 lt-s mode states ? g1 deactivated the line interface is not transmitting. there is no signal detected on the s interface, and no activation command is received in the c/i channel. ? g2 pending activation as a result of an info 1 detected on the s line or an ard command, the line interface begins transmitting info 2 and waits for reception of info 3. the timer to supervise reception of info 3 is to be implemented in software. in case of an arl command, loop 2 is closed. ? g3 activated normal state where info 4 is transmitted to the s interface. the line interface remains in this state as long as neither a deactivation nor a test mode is requested, nor the receiver looses synchronism. when receiver synchronism is lost, info 2 is sent automatically. after reception of info 3, the transmitter keeps on sending info 4. ? g2 lost framing this state is reached when the line interface has lost synchronism in the state g3 activated. ? g4 pending deactivation this state is triggered by a deactivation request dr. it is an unstable state: indication di (state g4 wait for dr.) is issued by the quat-s when: either info 0 is received, or an internal timer of 32 ms expires. ? g4 wait for dr final state after a deactivation request. the line interface remains in this state until a response to di (in other words dc) is issued. ? test mode 1 single alternating pulses are sent on the s interface (2 khz repetition rate). ? test mode 2 continuous alternating pulses are sent on the s interface (96 khz).
peb 2084 semiconductor group 45 3.4.2 lt-t mode (x) unconditional commands command / indication codes, conditional states commands (upstream) lt-t mode abbreviation code remark timing tim 0000 line interface is powered up reset rs 0001 (x) test mode 1 tm1 0010 transmission of pseudo-ternary pulses at 2 khz frequency (x) test mode 2 tm2 0011 transmission of pseudo-ternary pulses at 96 khz frequency (x) activate request, priority 8 ar8 1000 activation command, d channel priority is 8 activate request, priority 10 ar10 1001 activation command, d channel priority is 10 active request loop arl 1010 activation of loop 3 (x) deactivate indication di 1111 line interface is powered down
peb 2084 semiconductor group 46 indications (downstream) lt-t mode abbreviation code remark deactivate request dr 0000 deactivation request via s/t interface reset res 0001 reset acknowledge test mode 1 tm1 0010 tm1 acknowledge test mode 2 tm2 0011 tm2 acknowledge slip detected slip 0011 wander is larger than 50 m s peak- to-peak (or 25 m s peak-to-peak if programmed, refer to the c/w-bit of the configuration register) resynchronization during level detect rsy 0100 signal received, receiver not synchronous power up pu 0111 line interface is powered up activate request ar 1000 info 2 received activate request loop arl 1010 loop 3 closed code violation received cvr 1011 after each multiframe the receipt of at least one illegal code violation is indicated four times. this function must be enabled by setting the rcve-bit in the configuration register. activate indication loop ail 1110 loop 3 activated activate indication with priority class 8 ai8 1100 info 4 received, d-channel priority is 8 or 9 activate indication with priority class 10 ai10 1101 info 4 received, d-channel priority is 10 or 11 deactivate confirmation dc 1111 line interface is powered down
peb 2084 semiconductor group 47 figure 25 quat-s state diagram in the lt-t mode, unconditional states (transitions) note: 1) in state loop 3 activated, i3 is the internal signal, the external signal is i0.
peb 2084 semiconductor group 48 lt-t mode, conditional states ? f3 power down this is the deactivated state of the physical protocol. the receive line awake unit is active. ? f3 power up this state is similar to f3 power down. the state is invoked by a c/i command tim = 0000 (or di static low). after the subsequent activation of the clocks the power up message is output. ? f3 pending deactivation the line interface reaches this state after receiving info 0 (from states f5 to f8). from this state an activation is only possible from the line (transition f3 pend. deact. to f5 unsynchronized). the power down state may be reached only after receiving di. ? f4 pending activation activation has been requested from the terminal, info 1 is transmitted, info 0 is still received, power up is transmitted in the c/i channel. this state is stable: timer t3 (i.430) is to be implemented in software. ? f5/8 unsynchronized at the reception of any signal from the nt, the quat-s ceases to transmit info 1, adapts its receiver circuit, and awaits identification of info 2 or info 4. this state is also reached after the line interface has lost synchronism in the states f6 or f7 respectively. ? f6 synchronized when the quat-s receives an activation signal (info 2), it responds with info 3 and waits for normal frames (info 4). ? f7 activated this is the normal active state with the layer-1 protocol activated in both directions. from state f6 synchronized, state f7 is reached almost 0.5 ms after reception of info 4. ? f7 slip detected when a slip is detected between the t interface clocking system and the iom-2 interface clocks (phase wander greater than 50 m s, data may be disturbed, or 25 m s if programmed in the configuration register) the line interface enters this state, synchronizing again the internal buffer. after 0.5 ms this state is left again.
peb 2084 semiconductor group 49 lt-t mode, unconditional states the unconditional states should be left with the command tim. ? loop 3 closed on activate request loop command, info 3 is sent by the line transmitter internally to the line receiver (info 0 is transmitted to the line). the receiver is not yet synchronized. ? loop 3 activated the receiver is synchronized on info 3 which is looped back internally from the transmitter. data may be sent. the indication ail is output to indicate the activated state. when the s/t line awake detector, which is switched to the line, detects an incoming signal, this is indicated by rsy. ? test mode 1 single alternating pulses are sent on the t interface (2 khz repetition rate). ? test mode 2 continuous alternating pulses are sent on the t interface (96 khz). ? reset state a hardware or software reset (res) forces the line interface to an idle state where the analog components are disabled (transmission of info 0) and the t line awake detector is inactive. thus activation from the nt is not possible.
peb 2084 semiconductor group 50 3.4.3 example of activation/deactivation an activation and deactivation procedure between a quat-s and an isac-s or sbcx in te mode over the s/t interface line is shown in figure 26 . it illustrates how the state machines of the respective modes interwork to facilitate activation and deactivation. in this case activation was initiated by an ar request at the terminal side and deactivation by a dr command at the lt side. activation could also be initialized at the lt side using an ar request. figure 26 example of s/t interface activation and deactivation note: t1: 4 ms time for info 1 detection t2: 1 ms time for synchronization t3: 500 ms time for info 4 detection (2 subsequent frames) t4: 16 ms time for info 0 detection t5: 32 ms timer
peb 2084 semiconductor group 51 3.5 diagnostic functions, test loop-backs different test loops for b1, b2 and d-channels can be closed in the quat-s: C transparent analog loops (the data are also sent forward). C non transparent analog loops (the forward data path is blocked). C external transparent analog loop for board test. the loops may be closed in both operational modes, in lt-s and in lt-t, via the c/i command arl which may be applied (continuously) in the states g4 pending deactivation, g4 wait for dr and g1 deactivated. loop transparency can be achieved by setting the lp-bit in the configuration register. an example is shown in figure 27. figure 27 an example for quat-s in lt-s mode with a transparent loop (loop 2) and in lt-t mode with a non transparent loop (loop 3) loop 2 and 3 are activated over the iom-2 interface with activate request loop (arl).
peb 2084 semiconductor group 52 3.6 s and q channel access according to ccitt recommendation i.430 a multi-frame (= 20 consecutive s/t frames) provides an additional communication channel between te and lt or lt and co via s and q bits. refer to figure 28. two s channels (s1 and s2) can be used by the quat-s for communication in data downstream direction. the q channel bits are defined to be the bits in the f a bit position and are used for communication in data upstream direction. figure 28 direction of s and q channels in different application modes the following table shows the s and q bit positions within the multi-frame (20 s/t frames). frame number lt to te or co to lt te to lt or lt to co 1 2 s11 s21 q1 zero 6 7 s12 s22 q2 zero 11 12 s13 s23 q3 zero 16 17 s14 s24 q4 zero 1 s11 q1
peb 2084 semiconductor group 53 all other s and q bit positions within the remaining 12 frames of the multi-frame carry the value zero. the s and q bits are accessed by the elic or epic via iom-2 interface monitor channel. the bits are handled in byte format packed in the lower nibble. the upper nibble is used as identifier for the message type. the bit structure used by the quat-s is outlined in the following table. quat-s has implemented a 3 4 bit ram as buffer for the s and q bits. the 4-bit ram cells can be addressed separately. the data are handled by the quat-s in either non auto mode or in transparent mode. in the transparent mode the s data are transferred in downstream direction as a real time data stream of 1.600 bit/s (8 bits in 5 ms = 20 250 m s), the q data are transferred in upstream direction as a real time data stream of 800 bit/s (4 bits in 5 ms). in non auto mode the received s and q channels are checked for code changes and, if a change is detected, the new four bits are transferred. in transmit direction each of the 4-bit message is repeated until a new word is written into the buffer (e.g. into the mffifo in elic). 3.7 default-use of pin ceb/ssync the peb 2084, quat-s, uses the input signal at pin ceb/ssync as an external multiframe synchronization input in any case except if dcm(1:0) is set to 10 in any of the four channels. the external multiframe synchronization input signal is expected to be low for 125 m s and high for 2n + 1 times 125 m s thus defining an s/t interface multiframe of n + 1 frames. the edges of the external multiframe synchronization input signal have to be in coincidence with the rising edges of fsc. each low at this input will generate one frame with m-bit as binary ones at the s/t interface output. when setting bit mfd (configuration register) to 1, this function enables the generation of arbitrary multiframes, which may be useful to synchronize digital cellular wireless communications equipment. while using ssync for m-bit generation the short fsc signal is not allowed as it would reset the super-frame generated by ssync . if not used, the ssync input must be connected via a pull-up resistor to v dd . identifier downstream data upstream data 0 0 0 1 s11 s12 s13 s14 0 0 1 0 s21 s22 s23 s24 0 0 0 1 q1 q2 q3 q4
peb 2084 semiconductor group 54 4 registers description as the quat-s contains four peb 2081, sbcx, cores, it contains four complete register sets. all registers programming is done via the four iom monitor channels. access to the registers of the quat-s are treated as local functions and therefore are marked with the code 1000 in the first four bits of the message: monitor message: register read an internal register is read by setting the internal address to zero (0 h ) and indicating the address of the specific register in the bits d(3:0). the bits d(7:4) are set to zero. e.g. 80 h 01 h is the read command for the register 1 h , the configuration register. the response message from quat-s comprises two bytes, the first showing the address after the local function code, the second showing the register data. e.g. 81 h (d7:0) is the response to a read command on address 1 h , where d(7:0) is the content of the configuration register. register write an internal register is written by setting the internal address to the address of the specific register. the register will then be loaded with the value of d(7:0), e.g. 81 h 5d h programs the configuration register (addr. 1 h ) with the value 5d h . 4.1 identification register read, address: 0 h after the read command 80 h 00 h according to the procedure described above the quat-s transmits the response 80 h 44 h . the returned value 44 h of the identification register is specific for the peb 2084, quat - s. code = 1 0 0 0 internal address d7 d6 d5 d4 d3 d2 d1 d0 code = 1 0 0 0 0 0 0 0 0 0 0 0 register addr. = 01 h code = 1 0 0 0 register addr.= 01 h d7 d6 d5 d4 d3 d2 d1 d0 code = 1 0 0 0 register addr. d7 d6 d5 d4 d3 d2 d1 d0 bit 7 bit 0 format:01000100
peb 2084 semiconductor group 55 4.2 configuration register read/write, address: 1 h initial value: 00 h bit 7 bit 0 format: mfd rclk 0 lp sqm rcve c/w mode bit-name description mfd multi-frame disable (write): 0: all multi-frame functions active. 1: multi-frame generation (lt-s) or synchronization (lt-t) prohibited. no sq monitor messages released. multi-frame detected (read): 0: no multi-frame synchronization achieved. 1: multi-frame synchronization (lt-t) achieved. rclk receive clock 0: no output signal at pin clk1/ids (if all quat-s channels are programmed to 0 at this bit location, the output pin clk1 is tristated) 1: the 1.536 mhz clock synchronized to the receiver (lt-t) is output at the pin clk1(due to an internal short-circuit safety logic, a 1 is only processed if the other three channels are set to 0 at this bit location.) note: the pin clk1/ids is used to pin-strap the dcl data clock ratio during hw reset phase 10: double clock 11: single clock lp loop lt-s mode 0: transparent analog loop 1: non transparent analog loop lt-t mode 0: non transparent analog loop 1: external transparent loop sqm sq channel handling mode selection 0: non auto mode only s1 and q channels 1: transparent mode s1, s2 and q channels
peb 2084 semiconductor group 56 4.3 loopback register read/write, address: 2 h initial value: 02 h note: register bits not described may exist in hardware due to the use of the peb 2081, sbcx, core. writing those bits other than the default value will cause unexpected behavior of the device. rcve receive code violation indication (c/i) enable 0: normal operation 1: a code violation detector is implemented to support the far-end-code-violation (fecv) function according to ansi t1.605. after each multi-frame the receipt of at least one illegal code violation is indicated by the occurrence of four times the ci code 1011 (cvr). c/w configuration / wander detection lt-s mode: configuration 0: point-to-point or extended passive bus configuration (adaptive timing recovery). 1: short passive bus configuration (fixed timing recovery) lt-t mode: wander detection (warning on slip detection in c/i, data may be lost!) 0: slip after 50 m s wander 1: slip after 25 m s wander mode mode select 0: lt-s mode selected 1: lt-t mode selected bit 7 bit 0 format:0sb2sb100010 bit-name description sb2 loopback b2 channel at the s/t interface sb1 loopback b1 channel at the s/t interface bit-name description
peb 2084 semiconductor group 57 4.4 auxiliary register read/write, address: 4 h initial value: ci(3:0), 0 h note: register bits not described may exist in hardware due to the use of peb 2081, sbcx, core. writing those bits other than the default value will cause unexpected behavior of the device. bit 7 bit 0 format: ci3 ci2 ci1 ci0 tod 0 dcm1 dcm0 bit-name description ci(3:0) c/i codes as in c/i channel the indication can be read via monitor channel ci (3:0). tod time-out disable 0: monitor timeout (minimum 5 ms) 1: the time-out function of the monitor transmitter can be disabled to ease manual software debugging. dcm(1:0) d-channel mode: specific d channel associated functions including the pins drdy and ceb/ssync : 00: transparent d-channel, pins drdy and ceb/ssync tristated. 10: lt-t mode: d-channel collision resolution according to ccitt i.430. pin drdy conveys control information synchronous to d-channel timeslots to control peb 2075, idec (0: stop; 1: go). lt-s mode: d-channel access control by establishing a logical passive bus structure, where the received d-channel is anded with the other channels selected over pin ceb and the resulting value is sent back as echo bit. 11: lt-t mode: d-channel collision resolution according to ccitt i.430. pin drdy conveys asynchronous control information to control sacco-b in the elic, peb 20550. this mode is only applicable for a single channel lt-t application (0: go; 1: stop). lt-s mode: d-channel access control via the central d-channel arbiter unit of the peb 20550, elic. dependent on the command, each channel mirrors the received d-channel into the echo channel inverted command 1100 h ) or unchanged (1000 h ). 01: not applicable
peb 2084 semiconductor group 58 4.5 other registers other registers are implemented at address locations 3 h , 5 h , and 8 h . access to those monitor addresses may cause unexpected behavior of the device.
peb 2084 semiconductor group 59 5 electrical characteristics all characteristics given are valid under the following conditions unless otherwise indicated: t a = 0 to 70 c; v dd = 5 v 5 %; v ss = 0 v 5.1 absolute maximum ratings note: stresses above the listed values may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. parameter symbol limit values unit ambient temperature under bias t a 0 to 70 c storage temperature t stg C 65 to 125 c voltage on any pin with respect to ground v s C 0.4 to v dd + 0.4 v maximum voltage on any pin v max 6v
peb 2084 semiconductor group 60 line overload protection the maximum input current (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse. for the destruction current limits refer to figure 29. figure 29 maximum line input current for the receiver itd05400 5 50 500 5000 i ma 10 -9 -7 10 -5 10 -3 10 t sec
peb 2084 semiconductor group 61 5.2 dc characteristics pin parameter symbol limit values unit test condition min. max. all pins except sxna,b; srna,b xtal1, 2 input voltage v il C 0.4 + 0.8 v input high voltage v ih 2.0 v dd + 0.4 v output low voltage v ol 0.45 v i ol = 2 ma drdy, ido output low voltage v ol1 0.45 v i ol = 7 ma all pins except sxna,b; srna,b; xtal1, 2 output high voltage v oh 2.4 v i oh = C 400 m a v dd C 0.5 v i oh = C 100 m a input leakage current i li + 1 m a0 v v in v dd output leakage current i lo + 1 m a0 v v out v dd sxna,b absolute value of output pulse amplitude ( v sxna C v sxnb ) v x 2.03 2.10 2.31 2.39 v v r l = 50 w 1) r l = 400 w 1) sxna,b transmitter output current i x 7.5 13.4 ma r l = 5.6 w 1) sxna,b transmitter output impedance z x 10 0 k w w inactive or during binary one ( v dd = 0 5 v) during binary zero r l = 50 w srna,b receiver input impedance z r 30 100 k w w v dd = 5 v v dd = 0 v xtal1 input high voltage v ih 3.5 v dd + 0.4 v xtal1 input low voltage v il C 0.4 1.5 v xtal2 output high voltage v oh 4.5 v i oh = 5 m a, c 50 pf xtal2 output low voltage v ol 0.4 v i oh = 5 m a, c 50 pf note: 1) due to the transformers, the load resistance as seen by the circuit is four times r l .
peb 2084 semiconductor group 62 5.3 capacitances t a = 25 c; v dd = 5 v 5 %; v ss = 0 v; f c = 1 mhz dc characteristics (contd) pin parameter symbol limit values unit test condition min. max. power supply current operational i cc 55 ma v dd = 5 v inputs at v ss / v dd power down 5 ma no outputs loads, no xtal1 power down 10 ma no output loads, with xtal1 pin parameter symbol limit values unit min. max. all pins except sxn a, b pin capacitance c io 7pf sxn a, b output capacitance against v ss c out 10 pf xtal1, 2 external load capacitance c l 50 pf
peb 2084 semiconductor group 63 5.4 recommended oscillator circuits crystal nominal frequency: 7.68 mhz 100 ppm figure 30 recommended oscillator circuits 5.5 ac characteristics t a = 0 to 70 c; v dd = 5 v 5% ac testing: set-up, hold, delays inputs are driven at v dd C 0.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 2.0 v for a logic 1 and at 0.8 v for a logic 0. figure 31 input/output wave form for ac tests jitter the clock input fsc is used as reference clock to provide the 192 khz clock for the s/t interface. in the case of a desynchronous 7.68 mhz clock generated by an oscillator, the clock fsc should have a jitter of less than 50 ns peak-to-peak.
peb 2084 semiconductor group 64 5.6 clocks clk2 is directly derived from the oscillator clock and can drive up to 6 oscillator inputs of other communication ics, e.g. isac-s, peb 2085. figure 32 definition of clock period and width clk1 parameter symbol limit values unit test condition min. max. high phase of clock t wh 250 ns 50 pf load capacitance at clk1 low phase of clock t wl 250 ns 50 pf load capacitance at clk1 clock period t p 650.8 651.2 ns clk2 parameter symbol limit values unit test condition min. max. high phase of clock t wh 40 ns 50 pf load capacitance at clk2 low phase of clock t wl 40 ns 50 pf load capacitance at clk2 clock period t p 130.16 130.24 ns itt00766 3.5 v 0.8 v t wh t p t wl
peb 2084 semiconductor group 65 5.7 iom ? -2 interface timing figure 33 timing of the iom ? -2 interface with double data rate dcl note: 1) t ddf = 0.5 t dcl + t ddc C t fh timing characteristics of the iom ? -2 parameter symbol limit values unit conditions min. typ. max. frame sync hold t fh 30 ns frame sync setup t fs 70 ns frame sync high t fwh 130 ns frame sync low t fwl t dcl data delay to clock t ddc 100 ns data delay to frame 1) t ddf 150 ns data setup t ds 20 ns data hold t dh 50 ns
peb 2084 semiconductor group 66 figure 34 iom ? -2 interface timing with single data rate dcl note: 1) t ddf = 0.5 t dcl + t ddc C t fh timing characteristics of the iom ? -2 parameter symbol limit values unit conditions min. typ. max. frame sync. hold t fh 30 ns frame sync. setup t fs 70 ns frame sync. high t fwh 130 ns frame sync. low t fwl t dcl data delay to clock t ddc 100 ns data delay to frame 1) t ddf 150 ns data setup t ds 20 ns data hold t dh 50 ns
peb 2084 semiconductor group 67 figure 35 ssync timing parameter symbol limit values unit min. max. superframe sync. setup t ssys 200 ns superframe sync. hold t ssyh 200 ns
peb 2084 semiconductor group 68 5.8 timing of boundary scan test interface figure 36 boundary scan test interface timing parameter symbol limit values unit min. max. test clock period t tcp 160 ns test clock period low t tcpl 80 ns test clock period high t tcph 80 ns tms setup time to tck t mss 30 ns tms hold time from tck t msh 30 ns tdi setup time to tck t dis 30 ns tdi hold time from tck t dih 30 ns tdo valid delay from tck t dod 60 ns
peb 2084 semiconductor group 69 5.9 transceiver characteristics the transceiver comprises the transmitter output stages, the differential-to-single ended receiver input stage, the loop switch, the peak detector, and the threshold comparators. figure 37 transceiver architecture of one s/t-channel when transmitting a binary zero, the transmitter output is 2.1 v (difference between sxna and sxnb), when transmitting a binary one, it is tristate. the receiver input range is 2.5 v to 85 mv, the latter being a hardwired minimum peak level.
peb 2084 semiconductor group 70 transmitter performance cable 0.6 mm, 120 nf/km configuration condition distance te-te distance te-nt/lt point-to-point no noise C 980 m 200 / 2000 khz 100 mvpp C 940 m ext. passive bus no noise 120 m 720 m (roundtrip < 2 m s) 200 / 2000 khz 100 mvpp 120 m 540 m cable 0.6 mm, 30 nf/km configuration condition distance te-te distance te-nt/lt point-to-point no noise C > 1500 m 200 / 2000 khz 100 mvpp C > 1050 m ext. passive bus no noise > 250 m > 1250 m (roundtrip < 2 m s) 200 / 2000 khz 100 mvpp > 250 m > 800 m
peb 2084 semiconductor group 71 6 package outlines stand off plastic package, p-mqfp-44-2 (plastic metric quad flat package) gpm05622 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
peb 2084 semiconductor group 72 7 appendix list of transformer manufacturers and s 0 transformers the following list contains transformers recommended by different manufacturers for use with siemens s 0 transceivers. transformers marked with * have been tested in siemens s evaluation boards and have shown positive test results concerning pulse shape and impedance requirements of ets 300 012. manufacturers transformers apc apc 2040 s apc 1020 s apc 3060 s apc 9018 d apc 3366 d pulse engineering pe-68975* pe-64995 pe-65495 pe-65795 pe-68995 s + m components b78384-a1060-a2* b78384-p1111-a2 vacuumschmelze vac t60403-l4025-x021* t60403-l4097-x011* t60403-l5051-x006* t60403-l4021-x066 t60403-l4025-x095 t60403-l4097-x029 t60403-l5032-x002 valor pt 5001 pt 5069 st 5069 vogt 543 21 002 00* 543 21 004 00*

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